The present invention relates to a verifying apparatus of a data processing apparatus for fetching a command held in a command queue and executing and, more particularly, to a verifying method and apparatus of a data processing apparatus for holding a command in a command queue until the execution of the command is normally finished.
In recent years, in association with the realization of a high command executing speed by a CPU, not only is a command (synchronous command) sequentially executed in every machine cycle by a synchronous computing unit, but also a long command (asynchronous command), existing over a plurality of cycles, is executed in parallel with the operation of the CPU by providing an asynchronous computation control unit as another computing unit. A circuit scale of the data processing apparatus, therefore, increases by a size corresponding to only the asynchronous computation control unit. Problems such as failure of an LSI and defective logic operations occur. A necessity to improve the reliability is ever increasing.
FIG. 1 shows a conventional data processing apparatus. An asynchronous computation control unit 28 to execute a long asynchronous command in parallel is provided for a central processing unit (CPU) 26 having an integer computing unit 12 to sequentially execute commands. The command is decoded by a command control 10 provided in the CPU 26. In the case of a synchronous command, it is sent to the synchronous computing unit 12 and is executed. In the case of an asynchronous command, it is sent to the asynchronous computation control unit 28 and is executed. The asynchronous computation control unit 28 comprises: a command queue 14 to hold commands as a queue; a controller 25 to select the command which can be executed from the command queue 14; and an asynchronous pipeline computing unit 18 which functions as an asynchronous computing unit which receives the command selected and supplied from the command queue 14 by the controller 25 and executes the command in a plurality of cycles. As shown in FIG. 2, the command queue 14 is constructed by a command code 30, a first source register number 32, a second source register number 34, and a result register number (destination register number) 36.
When commands are generated from the command control 10 in the CPU 26, a queueing to temporarily hold the commands in the command queue 14 is executed. After completion of the queueing, the command which can be executed is selected by the controller 25 and is fetched from the command queue 14 and is supplied to the asynchronous pipeline computing unit 18. When there is a command preserving request in this instance, the command is held in the command queue 14 until the asynchronous pipeline computing unit 18 correctly finishes the execution of the command. When there is no command preserving request, the command is deleted from the command queue 14.
In case of providing an asynchronous computation control unit in order to realize a high computation processing speed, however, the circuit scale of the data processing apparatus increases by an amount corresponding to such an asynchronous computation control unit, so that a possibility of the occurrence of an LSI failure or defective logic operation is high. That is, when the pipeline control of the asynchronous calculations based on the command queue 14 provided in the asynchronous computation control unit 28 is disturbed by the occurrence of a defective LSI, failure, disconnection of wire, defective logic operation, or the like, the contents of the command queue 14 which holds the commands as a queue cannot be guaranteed. There is consequently a problem such that the data processing apparatus doesn't operate in accordance with the order of the command queue and a contradiction occurs in the execution of the commands and the execution of the commands is abnormally finished.